Binary rate multipliers for multiplying a train of pulses by a selectable calibration factor between zero and unity are well known. Such rate multipliers are used in many systems, mainly in various types of communication systems, where there is a need to create a new system frequency clock from a given higher-frequency clock. For example, one can derive the commercial standard clock frequency of 16.384 MHz from the cellular standard clock frequency of 16.8 MHz by multiplying the latter with the factor 512/525. The resulting frequency can be used for voice sampling at 8.0 kHz. Rate multipliers are also used in measurement devices such as a tachometer to transform a pulse train representing actual hardware units into engineering units such as meters or feet. Here, we will use clock frequencies for simplicity of explanation.
Prior art rate multipliers usually employ several counters which are combined in a specific way to provide the multiplication of the input pulse train. The single pulses of the result pulse train are like the single pulses of the input pulse train but some full or half cycles are missing per time unit according to the given multiplication factor. The ratio of the result frequency B and the input frequency A can be represented as a whole fraction number ##EQU1## where x, y, z are whole numbers representing cycles, and x is the number of cycles to be eliminated during y input cycles.
A prior art solution is to translate this ratio into a polynomial of simple fractions and use basic mathematical operators (like addition, subtraction and multiplication). This polynomial is implemented by a small number of counters which give as a result the primary ratio. As a numerical example it is assumed that a system clock CLK.sub.-- SYS of frequency B=16.384 MHz is wanted and a source clock CLK.sub.-- IN of frequency A=16.8 MHz is provided, which gives a frequency ratio of z/y=512/525, and x=13. The polynomial which represents this fraction can be written as: EQU 512/525=(525-13)/525=1-(1/35*(1-(1/5*(1-1/3)))). (2)
FIG. 1 shows prior art binary rate multiplier 10 requiring three counters (:35-counter, :5-counter and :3-counter) 12, 14, 16 and three subtractors 18, 20, 22. Source clock CLK.sub.-- IN 24 of frequency A=16.8 MHz is submitted to subtractor 18 and counter 12, which is a divided by 35-counter, i.e. for every thirty-five cycles at its input 26 it provides one cycle at its output 28, which means a total output of fifteen cycles every 525 input cycles. This :35-counter output signal is submitted to subtractor 20 and counter 14, which is a divided by 5-counter, i.e. for every five cycles at its input it provides one cycle at its output, which means a total output of three cycles every 525 input cycles. This :5-counter output signal is submitted to pulse train input 32 of subtractor 22 and counter 16, which is a divided by 3-counter, i.e. for every three cycles at its input it provides one cycle at its output, which means a total output of one cycle every 525 input cycles. The output signal of counter 16 is fed to subtraction input 30 of subtractor 22.
Subtractors 18, 20, 22 each have a pulse train input, a subtraction input and an output, and work as follows. A pulse on the pulse train input is submitted to the output if no pulse appears on the subtraction input, and is not submitted to the output if a pulse appears on the subtraction input. Assuming generally a logic that counts "one"-phases as pulses, source clock CLK.sub.-- IN 24 and all derived/divided signals consist of pulses that have "one"-phases of about the same length. Then, on every pulse at the subtraction input one pulse is "subtracted" from the output pulse train. Therefore, subtractor 22 outputs two cycles every 525 source clock cycles; subtractor 20 outputs thirteen cycles every 525 source clock cycles, and subtractor 18 outputs 512 cycles every 525 source clock cycles at rate multiplier-output 34. Thus, the source clock frequency CLK.sub.-- IN is divided by 512/525 and a system clock signal CLK.sub.-- SYS of the divided frequency is provided.
The resulting pulse trains of rate multipliers can be seen as consisting of source clock cycles and missing cycles, here called distortions. FIG. 2 shows a typical binary rate multiplier timing diagram. Source clock CLK.sub.-- IN provides continuous pulse train 36 that consists of symmetric pulses 38. Divided system clock signal CLK.sub.-- SYS 39 consists of symmetric pulses 40 and missing cycles 42, thirteen cycles are missing every 525 source clock cycles.
Often, these missing cycles are not uniformly distributed in the pulse train. Often, the multiplication factor is fixed and a change in this factor makes it necessary to re-design a new binary rate multiplier.
There is a need for simple, economical rate multipliers; for rate multipliers that provide pulse trains with uniformly distributed distortions; and for rate multipliers that allow an easy change of the multiplication factor.